Appeal No. 96-0506
Application 07/856,001
OPINION
We reverse.
Appellant argues that neither Okamoto nor Chapman teaches or suggests the concept of
padding bit arrays with bits having constant values as required to symbol align such arrays for plural
"scan patterns" (Brief, pages 5-6). The examiner apparently admits that neither Okamoto nor
Chapman teaches padding, but states in the response to the arguments section (Examiner's Answer,
pages 7-8):
Appellant has argued that the cited references do not teach padding to provide symbol aligned
arrays of bits. However, it is well known in the art to pad bits; it would have been obvious
to one of ordinary skill in the art to modify the cited references because one of ordinary skill
in the art would have wanted to ensure the correct communication and/or storage of
information. For examples of padding of bits/bytes, see the four references included as part
of the final action paper #5, mailed 10/7/94.
The examiner does not explain how the general use of padding bits in the prior art suggests or makes
obvious the specific padding recited in claim 1. The examiner relies on Cerracchio, Patel, Golden,
and Pughe to show padding. However, we cannot consider the merits of these references because
they have not been denominated as a part of the rejection. A rejection must expressly mention the
references relied on. In re Hoch, 428 F.2d 1341, 1342 n.3, 166 USPQ 406, 407 n.3 (CCPA 1970)
("Where a reference is relied on to support a rejection, whether or not in a 'minor capacity,' there
would appear to be no excuse for not positively including the reference in the statement of the
rejection."). Procedural due process and 35 U.S.C. § 132 of the patent statute require that applicants
be adequately notified of the reasons for the rejection of claims so that they can decide how to
proceed. See In re Ludtke, 441 F.2d 660, 662, 169 USPQ 563, 565 (CCPA 1971). Knowing exactly
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