Ex parte GUTTAG et al. - Page 2




          Appeal No. 96-3494                                                          
          Application 08/160,299                                                      


          This is a decision on the appeal under 35 U.S.C. § 134                      
          from the examiner's final rejection of claims 1-34, which                   
          constitute all the claims in the application.  Appellants have              
          indicated that the appeal is withdrawn with respect to claim                
          34 [brief, page 2].  Accordingly, this appeal now involves                  
          only claims 1-33.                                                           
          The claimed invention pertains to a data processing                         
          apparatus having an arithmetic logic unit (ALU) with three                  
          separate multibit digital inputs.  The ALU performs mixed                   
          arithmetic and Boolean operations on the three inputs.  A                   
          barrel rotator is connected to one of the three inputs for                  
          rotating the digital signal received at that input.  A                      
          function control input to the ALU determines which operations               
          will be performed on the three multibit digital inputs                      
          received by the ALU.                                                        
          Representative claim 1 is reproduced as follows:                            
               1.  A data processing apparatus comprising:                            
               an arithmetic logic unit having first, second and                      
          third data inputs for multibit digital signals representing                 
          corresponding first, second and third input signals, and a                  
          function control input signal for receiving a function signal,              
          said arithmetic logic unit generating at an output a multibit               
          digital signal representing a mixed arithmetic and Boolean                  
          combination of said first, second and third inputs                          
                                          2                                           





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