Appeal No. 97-1784
Application 08/011,068
DECISION ON APPEAL
This is a decision on appeal from the final rejection
of claims 1 through 20, all of the claims pending in the present
application.
The invention relates to a clock generation circuitry
that provides clock signals with controlled duty cycles.
The independent claim 1 is reproduced as follows:
1. A digital clock waveform generator comprising:
a variable delay circuit including an input line, an
output line, a propagation path coupled between said input line
and said output line, and a control line, wherein said variable
delay circuit is configured such that a propagation delay of said
propagation path between said input line and said output line is
variably controllable in response to a control signal provided to
said control line;
a control unit coupled to the control line of said
variable delay circuit and configured to iteratively adjust the
propagation delay of said variable delay circuit such that a
period of a timing signal provided to said input line of said
variable delay circuit is coverged [sic, converged] upon by the
propagation delay of said variable delay circuit; and
a signal synthesis circuit coupled to a node connected
to the propagation path of said variable delay circuit, wherein
said signal synthesis circuit is configured to generate a clock
signal having a duty cycle and a period that are dependent upon
signal transitions between a high logical state and a low logical
state occurring at said node connected to the propagation path of
said variable delay circuit.
The Examiner relies on the following references:
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