Appeal No. 94-3710
Application 07/777,608
stored in said step (c) and said first segment entry stored in
said step (e) in said segment descriptor cache;
(g) if the segment descriptor stored in the first entry
in said data cache is altered by said data processing unit,
checking said inclusion bit in said data cache; and
(h) flushing said entire segment descriptor cache if
said segment descriptor in said first format with a set
inclusion bit has been altered.
Opinion
We do not sustain the rejection of claims 1-6 under 35
U.S.C. § 103 as being unpatentable over Kaplinsky and
Cepulis.
This decision is based solely on the rationale as
articulated by the examiner. We do not express an opinion on
rationales not articulated by the examiner.
A. Kaplinsky is not directed at maintaining
the coherency of a segment descriptor cache
According to the examiner, "Kaplinsky teaches a system
for maintaining cache coherency between a data cache and a
descriptor cache in a memory management system of a computer
comprising a descriptor table (Figure 5) and a data cache for
storing segment descriptors in a first format (Figures 8A and
8B)." Examiner's Answer, at 3. In the examiner's view, the
"presence bit" in Kaplinsky constitutes an "inclusion bit" for
5
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