Appeal No. 94-4342
Application No. 07/765,771
boundary portion thereof is not overlapped by said first
conductor over the major surface of said semiconductor
substrate,
wherein said step of implanting said impurities comprises
spacing said impurities laterally from said first conductor by
said lateral thickness of said sidewall insulating film and
thereby separating said impurities laterally from said first
conductor by a distance corresponding to said predetermined
vertical thickness of said third insulating film.
As evidence of obviousness, the examiner relies on the
following prior art:
Horiuchi et al. (Horiuchi) 0171003 Feb. 12, 1986
(Published European Patent Application)
Appellants’ admitted prior art, figures 13A-13G and 14 and
their description at pages 6 through 8 of the specification
(hereinafter referred to as “admitted prior art”).
Claims 10, 11, 14 and 15 stand rejected under 35 U.S.C.
§ 103 as unpatentable over the admitted prior art in view of
Horiuchi.
Having carefully considered the entire record before us,
including all of the arguments advanced by the examiner and
appellants in support of their respective positions, we find
ourselves in complete agreement with the position succinctly
set forth by appellants in their Brief, pages 7 and 8, and
Reply Brief, pages 1 and 2. As indicated by appellants, the
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