Appeal No. 95-4531
Application No. 07/939,892
pulse signal at an input node to a second voltage level at an
output node coupled to a capacitive load.
Claim 1 is illustrative of the claimed invention, and it
reads as follows:
1. A level shift circuit for a logic circuit for
translating a first voltage level binary pulse signal from said
first voltage level at an input node to a second voltage level at
an output node coupled to a capacitive load, said circuit
comprising:
a resistor connected to a DC supply voltage;
diode means with a capacitance substantially higher than
that of the capacitive load for creating the voltage level
translation connected in series with said resistor and having a
first and a second terminal, wherein said second terminal forms
said output node at the point of interconnection of said resistor
and said diode means;
said first voltage level binary pulse signal connected to
said diode means at said first terminal which is said input node,
and said second voltage level pulse signal appearing at said
output node.
The references relied on by the examiner are:
Davis 3,535,546 Oct. 20, 1970
Eden 2,166,312 Apr. 30, 1986
(U.K. patent application)
Sedra et al. (Sedra), “Microelectronic Circuits,” Holt, Rinehart
and Winston, Inc., pages 170, 171, 195 and 453, 1987.
Claims 1, 2, 4 through 9, 14 through 24 and 26 stand
rejected under 35 U.S.C. § 103 as being unpatentable over Sedra
in view of Eden.
Claims 3, 10 through 13 and 25 stand rejected under
2
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