Appeal No. 95-5064
Application 08/049,463
All of the appealed claims (i.e., claims 1-3 and 5-8)
stand rejected under 35 U.S.C. § 103 as unpatentable for
obviousness over Konopka. Although Appellant's brief states
(at 4) that the claims do not stand or fall together, the only
claim that is specifically argued in the brief is claim 1.
Accordingly, we will treat claims 2, 3, and 5-8 as standing or
falling with claim 1. In re King, 801 F.2d 1324, 1325, 231 USPQ
136, 137 (Fed. Cir. 1986).
Konopka discloses a circuit for shutting down a PWM
(pulse width modulation) power supply 16 (Fig. 1) when a low
voltage detector 20 determines that the input DC voltage ("HIGH
DC") at power supply input terminal 15 drops below a
predetermined level for a predetermined period of time (e.g.,
13 ms). Under these circumstances, the low voltage detector 20
outputs a signal via a latch circuit 22 to a shut down circuit
24, which issues a PWM OFF signal and a DATA SAVE signal.
Referring to Figure 2, which shows the details of the low voltage
detector 20, the collector of transistor 40 is at ground
potential when the input DC voltage at terminal 15 is at or above
an acceptable level. When the input voltage drops below that
level, the collector voltage increases, causing capacitor 38 to
charge through resistor 36. If the input voltage remains low for
-3-
Page: Previous 1 2 3 4 5 6 7 Next
Last modified: November 3, 2007