Appeal No. 96-1588
Application 08/036,947
under 35 U.S.C. § 103. Claims 3-6, 9-12, 15-18, 20, 22, and 24
stand objected to for depending on rejected claims. We reverse.
The invention relates to a computer system that supports
multiple instruction issues and, more particularly, to a method
of instruction scheduling performed by compilers targeting such
computer systems. In scheduling instructions, the method of the
invention distinguishes between, inter alia, "squeezed" and "non-
squeezed" instructions. The specification (at 4) defines a
squeezed instruction as an instruction that cannot be scheduled
for parallel execution with any other instructions on the
targeted machine and a non-squeezed instruction as an instruction
that can be scheduled for parallel execution with at least one
other instruction on the targeted machine.
Appellant's Figure 8a shows an example of two four-
instruction chains made up of Add, Multiply, and Divide
instructions. The first chain consists of instructions "instr-1"
through "instr-4" and the second chain of instructions "instr-5"
through "instr-8." As explained in the paragraph bridging pages
16 and 17, the Add and Multiply instructions are non-squeezed and
the Divide instruction is squeezed. The schedule size is
initially selected to be as small as possible without considering
the squeezed (i.e., Divide) instructions (page 17, lines 11-15).
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