Appeal No. 96-1588
Application 08/036,947
simulation time are moved to the Ready Set (step 62) (col. 11,
lines 19-29). If the Ready Set is empty (step 44) and the Leader
Set is empty (step 54), all of the instructions have been
scheduled and the process ends; if the Ready Set is not empty
(step 44), the instruction in the Ready Set having the highest
cost is scheduled (step 46) and its node and outward edges are
removed from the DAG (step 48) (col. 11, lines 33-39). The
simulation time is then advanced to the point in time at which
the just issued instruction would issue (step 64) (col. 11, lines
40-42). The machine resources such as registers and the
functional unit are assigned to the scheduled instruction at step
50, and any new interlocks caused by the assignment of machine
resources are checked to see if instructions in the Ready Set
need to moved back into the Leader Set (step 52) (col. 11, lines
42-48). The process then returns to the beginning, to schedule
the next instruction (col. 11, lines 48-49).
The examiner concedes that Rasbold does not expressly
characterize his instructions as squeezed and non-squeezed, but
argues that "it would have been obvious to a person of ordinary
skill in the art that the claimed squeezed/(not squeezed)
instructions are not more than the dependent/independent
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