Appeal No. 96-1979
Application 08/041,770
The invention is directed to an apparatus and method for fault tolerant operation of a
multiprocessor data processing system. More particularly, the invention concerns the identification of a
failed master processor and the subsequent designation of a new master processor for the failed master
processor. The identification is said to be performed in a “dynamic” manner wherein a contention
operation is utilized such that each processor contends with other processors to become the new
master processor by writing its tag on all of the processors in the system. Once a processor has tagged
each of the operating processors, it declares itself the new master by, for example, writing a master
identification tag on each processor. Only a single new master processor will be declared.
Independent apparatus claim 1 is reproduced as follows:
1. A fault tolerant multiple processor data processing system, comprising:
a plurality of processors including a master processor which coordinates the operation of said
plurality of processors;
means for connecting said plurality of processors to form a local area network;
a plurality of memory devices coupled to said plurality of processors;
means for identifying a failure of said master processor; and
means for assigning a new master processor from said plurality of processors, in a dynamic
manner, after said failure of said master processor, said assigning means including means for executing a
contention operation wherein each processor of said plurality of processors contends to become said
new master processor by attempting to write a tag on each processor of said plurality of processors.
The examiner relies on the following references:
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