Appeal No. 96-3124
Application 08/265,585
The invention relates to fault-tolerant multiple
processor systems. In particular, the invention is directed
to a technique
that permits the system to recover from momentary or very
short drops in primary power that may be noticed by fewer than
all of the processors.
The independent claim 3 is reproduced as follows:
3. A processing system composed of a plurality of
processor units interconnected for communicating messages
there-between, including presence messages sent by each
of the plurality of processor units to the plurality of
processor units during a regroup operation to determine
the plurality of processor units of the processing
system, each of the plurality of processor units having a
source of power and a detector element for monitoring the
source of power for power-fail situations to produce a
power-fail signal indicative of a possible impending
failure of the source of power, and responsive to the
power-fail signal each of the processor units performing
the steps of:
broadcasting a power-fail message to the
plurality of processor units indicating receipt
of the power-fail signal;
recording receipt of the power-fail message; and
during a regroup operation, checking for a
recordation of a prior received power-fail
message, and if the recordation exists sending a
2
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