Appeal No. 96-4106
Application No. 08/271,238
the copy processor unit lags the operation of the checked
processor unit by at least one clock period.
Claims 26 and 35 are illustrative of the claimed
invention, and they read as follows:
26. A self-checking processor system, comprising:
first and second processor units each operating in
response to instructions to produce address and data signals;
memory means for supplying the instructions to the first
processor unit in response to address signals from the first
processor unit;
first bus means coupling the memory means to the first
processor unit for communicating address and data signals
therebetween;
first circuit means, including second bus means, coupling
the first bus means to the second processor unit for
communicating to the second processor unit data signals from
the first bus means in a manner emulating the memory means to
the second processor unit; and
second circuit means coupled to first circuit means to
receive and compare address and data signals produced by the
first processor unit to address and data signals produced by
the second processor unit to assert an error signal when a
miscompare is detected.
35. A method of operating first and second substantially
identical digital circuits to use the first digital circuit as
a check for proper operation of the second digital circuit,
the second digital circuit operating in response to a periodic
clock signal to receive data and to supply therefrom second
data in execution cycles measured by the periodic clock
signal, the method comprising the steps of:
3
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