Appeal No. 97-4407
Application 08/441,560
DECISION ON APPEAL
This is a decision on appeal from the final rejection
of claims 1 through 7, all of the claims pending in the present
application.
The invention relates to electronic testing of digital
integrated circuits. Appellant discloses on page 5 of the
specification that Figure 1 is a system block diagram
illustrating a general configuration of an addressable serial
test system in accordance with a preferred embodiment of the
invention. Serial shift or serial access register 103 is used to
serially transfer both address and data for both controlling and
observing internal logic nodes of a digital system. A data
stream containing address and data information is serially
applied to scan input 104 and clocked into serial access register
103. Once register 103 is loaded, the address information is
applied to address bus 101 and data information is applied to a
global bi-directional data bus 100.
The address is used to specify which subset of a
multiplicity of subsets of the internal logic nodes are to be
2
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