Appeal No. 97-4407
Application 08/441,560
1237, 1239 (Fed. Cir. 1995), cert. denied, 117 S.Ct. 80 (1996)
citing W. L. Gore & Assocs., Inc. v. Garlock, Inc., 721 F.2d
1540, 1548, 220 USPQ 303, 309 (Fed. Cir. 1983), cert. denied,
469 U.S. 851 (1984).
Appellant argues on pages 3 and 4 of the brief that
Edwards fails to teach or suggest a storage element having a
selection signal input coupled to the load output of the address
decoder and a test data input element coupled to another portion
of the plurality of outputs of the serial shift register. Appel-
lant points out that with the claimed structure any data can be
forced into the storage element in a test mode, where in the
Edwards system the storage element can only be forced to one
fixed logical state.
We note that Appellant’s independent claims 1, 4 and 6,
all recite the above structure as argued by Appellant. In par-
ticular, Appellant's claim 1 recites "a storage element having a
clock input coupled to the system clock signal, a data input
residing at a logical state [and] an output." We note that
Edwards teaches a storage element as shown in Figures 1A and 3
6
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