Appeal No. 95-3557
Application No. 07/833,417
Huster uses a diffused and/or ion-implanted layer to form the pn-junction, resulting in a substantial
reduction in process complexity. Using two diffusions of distinctly different penetration depths, Huster
obtained a vertical membrane structure having thinner membranes (i.e., flexure sections) suspended on
thicker rims (i.e., boss sections) of arbitrary shape, thereby achieving improved stability of the
suspension of very thin membranes. Huster describes using “standard” integrated circuitry (IC)
processing steps, e.g., boron doped silicon wafers with 11-16 ohm cm resistivity were subjected to
standard integrated circuitry processing to provide pn-junctions, patterns, contacts and masking layers.
Junctions of thicknesses ranging from 3 to 12 µm were formed using a standard POCl diffusion
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process at 1000E C or phosphorus ion implantation for predeposition followed by a drive-in diffusion at
1100E C. The wafers were etched in 40% KOH solution at 50E C with a potential of + 1.5 V at the
n+ diffusion to provide etched membranes of typically 5 and 15 µm thicknesses, respectively. (See
pages 899-901 and Figs. 1-7.) As noted in the specification, an annealing step is conventional after
high energy implantation to eliminate crystal lattice defects and to diffuse dopants to the proper depth
(page 7, last para.). Appellants have not challenged the examiner’s finding that “specific resistivity,
annealing temperature and thickness of coating layer” are art-recognized result-effective variables
subject to routine experimentation and optimization (answer, page 9). Given the equivalency of
epitaxial layer and diffusion/ion-implantation layers in forming the pn-junction suggested by Huster and
the use of standard IC procedures for processing, masking, etching, etc. in Huster, it reasonably
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Last modified: November 3, 2007