Appeal No. 96-2237
Application 08/113,509
THOMAS, Administrative Patent Judge.
DECISION ON APPEAL
Appellant has appealed to the Board from the exam-
iner's final rejection of claims 14 through 26, which consti-
tute all the claims remaining in the application.
Representative claim 20 is reproduced below:
20. In a data processing system having a processor,
a data memory, an instruction memory, an address bus, a data
bus, an instruction bus, and a control bus, a method for
accessing said data memory and said instruction memory, said
method comprising the steps of:
placing on said address bus a first address which is
either an instruction address or a data address, and placing
on said control bus a first value indicating whether said
first address is an instruction address or a data address;
latching said first address in either said instruc-
tion memory or said data memory, as designated by said first
value;
ceasing to place said first address on said address
bus and ceasing to place said first value on said control bus;
placing on said address bus a second address which
is the other of an instruction address and a data address, and
placing on said control bus a second value indicating whether
said second address is an instruction address or a data ad-
dress;
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