Appeal No. 96-2237
Application 08/113,509
state that a "burst-mode access allows multiple instructions
or data words at sequential addresses to be accessed with a
single address transfer." The argument is not coextensive
with the teaching in the reference and the showing in Figure
6. The first appearance of INSTR N on the instruction bus
line in this figure does occur before the end of the address
existing on the corresponding address line, however, the
access is not complete until all of the retrieved instructions
have been
"accessed" by the processor. It is thus apparent that the
address does end on the address bus well before the entire
access cycle for the instruction is completed. A correspond-
ing data read operation in the burst-mode access would yield
the same
result.
Nor are we persuaded otherwise by the language at
the end of claim 20 which indicates that the first address is
either an address for a single instruction word or an address
for a single data word. Clearly, to the artisan, a single
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