Appeal No. 96-3054
Application 08/134,147
elected invention.
The invention relates to a phase-locked loop circuit
(PLL) for locking the phase of an oscillator output signal to
the phase of a reference signal by detecting a phase
difference through multiple clock cycles. In particular,
looking at Figure 8, the phase-locked loop includes a multi-
cycle phase detector 11, a charge pump 12, a loop filter 13
and a voltage controlled oscillator (VCO). The multi-cycle
phase detector 11 detects a phase difference between a
reference clock signal (input clock) from an off-chip source,
and the generated clock signal from the VCO on line 30. The
charge pump 12 connects to the phase detector 11 and provides
output current pulses to increase or decrease the output
voltage at the loop filter 13. The output voltage from filter
13 in turn adjusts the phase of the VCO.
Representative independent claim 15 is reproduced as
follows:
15. A phase-locked loop circuit for locking the
phase of an oscillator output signal to the phase of a
reference signal, comprising:
2
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