Appeal No. 96-3372
Application No. 07/823,153
data blocks in the first frame, the 3/5 voting logic circuit
also including means for storing the bit-wise voting result;
a decoding circuit which receives on a bit-by-bit basis
the bit-wise voting result from the 3/5 voting means of the
3/5 voting logic circuit and generates a first frame syndrome
at the end of the fifth data block of the first frame, the
decoding circuit also creating first frame correction
information during the first repeated data block of a second
frame;
a correction circuit which receives the first frame
syndrome and the correction information from the decoding
circuit during the first repeated data block of the second
frame and produces a decoding result and a bit correction
signal; and
a data buffer which receives during the first repeated
data block of the second frame the bit-wise voting result from
the 3/5 voting logic circuit and the bit correction signal
from the correction circuit, the data buffer utilizing the bit
correction signal to correct the bit-wise voting result to
produce corrected data which is loaded into the data buffer
and subsequently output as a corrected first frame data
stream during the first repeated data block of the second
frame.
The examiner relies on the following references:
Shishikura et al. (Shishikura) 4,675,868 June 23, 1987
Kikuchi 4,794,601 Dec. 27, 1988
Sharpe et al. (Sharpe) 4,965,820 Oct. 23, 1990
Claims 8-18 stand rejected under 35 U.S.C. § 103. As
evidence of obviousness the examiner offers Sharpe in view of
Kikuchi and Shishikura. A rejection of claims 8-18 under the
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