Appeal No. 1996-3391 Page 3
Application No. 08/160,573
and Boolean combination including at least one combination
performing a Boolean function prior to an arithmetic function;
a first data source supplying a first multibit digital
signal to said first data input of said arithmetic logic unit;
a second data source supplying a second multibit digital
signal;
a shifter having a data input connected to said second
data source, a shift control input receiving a shift control
signal, and a data output connected to said second data input
of the arithmetic logic unit, said shifter shifting said second
multibit digital signal an amount corresponding to said shift
control signal and supplying said shifted second multibit
digital signal to said second data input of said arithmetic
logic unit;
a third data source supplying a third multibit digital
signal to said third data input of said arithmetic logic unit.
The examiner relies on the following references:
Chu et al. (Chu) 4,785,393 Nov. 15,
1988
Ing-Simmons et al. 5,239,654 Aug. 24,
1993
Ing-Simmons (filed Nov. 17, 1989)
Claims 1 through 37 stand rejected under 35 U.S.C. 103 as
unpatentable over Ing-Simmons in view of Chu.
Reference is made to the briefs and answer for the
respective positions of appellants and the examiner.
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