Appeal No. 96-4080
Application 08/396,541
application. In an amendment filed after the final rejection
entered by the Examiner, claims 2 and 28 have been canceled
and claims 3, 13, 29 and 39 have been amended. Therefore,
claims 1,
3 through 27 and 29 through 52 are properly before us for our
consideration.
The invention relates to a microelectronic integrated
circuit including a plurality of hexagonal CMOS "NAND" gate
devices. On pages 4 through 7 of the specification, Appellant
discloses that Figure 2 is an electrical schematic diagram
illustrating Appellant's invention connected to provide a
logical NAND function. In particular, Appellant discloses
that gate device 30 includes a logical "ALL" element 133
having a hexagonal periphery 134 and a logical "ANY" element
233 having a hexagonal periphery 234. Appellant further
discloses that in order to minimize the area required on the
substrate 32 by the gate device 30, the logical "ALL" element
133 and the logical "ANY" element 233 are closely packed, with
the peripheries 134 and 234 having a common edge. As
illustrated in Figure 2, the edge 134-4 of the element 133 is
2
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