Ex parte NAKAMURA - Page 5




          Appeal No. 96-4081                                                          
          Application 08/417,333                                                      



          nowhere is it taught that the cells have only a single                      
          transistor.                                                                 
                    Turning to Appellant's specification, we find on                  
          page 1 that Appellant discloses that the present invention                  
          relates to a semiconductor memory device in which a single                  
          memory cell                                                                 
          consists of a single field effect transistor.  Furthermore,                 
          Appellant discloses on the same page that Figure 24 is a                    
          circuit diagram of a conventional semiconductor device having               
          a single memory cell provided by a single enhanced type Metal               
          Oxide Semiconductor (MOS) transistor.  Furthermore, on page 2               
          of the specification, Appellant discloses the operation of the              
          semi- conductor device shown in Figure 24 in which it clearly               
          shows that each transistor operates as a single cell to record              
          a  single bit of data.  On page 16 of the specification,                    
          Appellant discloses that Figure 1 is a circuit diagram of                   


          the present invention in which the eight transistors 51-58 are              
          enhanced type MOS transistors which each operate as a single                
          cell of the memory.                                                         

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