Appeal No. 96-4088
Application 08/317,411
ing element to generate parity for one message while simulta-
neously checking parity of the other message.
Independent claim 1 is reproduced as follows:
1. A processing array comprising:
a plurality of processing elements; and
a bidirectional interconnection network disposed to
directly connect all of adjacent neighboring processing ele-
ments for each of said plurality of processing elements for
carrying
data messages between any of the adjacent neighboring process-
ing elements,
wherein each of said processing elements of said
plurality of processing elements comprises:
a parity generating circuit for generating a parity
bit for a first data message that is transmitted by that
processing element over the interconnection network to another
processing element among said plurality of processing ele-
ments; and
a parity checking circuit for checking parity of a
second data message as it is received by that processing
element over the interconnection network, said parity checking
and parity generating circuits being separate from each other
and enabling that processing element to generate parity for
the first data message being sent by that processing element
while simulta- neously checking parity of the second message
being received by that processing element.
The Examiner relies on the following references:
Sze 4,346,474 Aug. 24, 1982
Chin et al. (Chin) 4,823,347 Apr. 18, 1989
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