Appeal No. 96-4088
Application 08/317,411
suggests "an output data path disposed to directly connect to
all of adjacent neighboring processing elements . . . a parity
checking circuit connected to the input data path, said parity
checking circuit checking parity of the second data message as
said second data message is received over the input path and
while the first data message is being sent out over the
output data path" as recited in Appellant's claim 8.
Appellant further emphasizes on pages 7 through 9 of the brief
that not all of the recited steps are described or suggested
by the combination of Sze and Chin.
Upon a close review of both Sze and Chin, we agree
that not all the claim elements are described or suggested by
the combination of Sze and Chin. In particular, we note that
Sze teaches an even-odd parity checking for synchronous data
transmission. In column 3, lines 5-30, Sze discloses that
Figure 1 illustrates a representative communications system
in which the present inventive improvement may be used. In
particular, Sze discloses three data receiving and
transmission
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