Appeal No. 1997-0515
Application 08/350,504
a gate insulating layer and gate electrode overlying
the epitaxial silicon region, wherein a channel region is
formed under the gate electrode in said epitaxial silicon
region;
sidewall insulating regions disposed alongside said
gate electrode;
lightly doped source/drain regions in said epitaxial
silicon region and said substrate underneath said sidewall
insulating regions and adjacent the channel region;
highly doped source/drain regions in said doped
substrate region and said epitaxial silicon region adjacent
the lightly doped source/drain regions, each of said highly
doped source/drain regions extending from an upper surface of
said epitaxial silicon region into said doped substrate re-
gion; and
a threshold adjust impurity region within the chan-
nel region.
The Examiner relies on the following references:
Kotani et al. (Kotani) 4,242,691 Dec. 30, 1980
Shibata et al. (Shibata) 4,939,386 July 3, 1990
Nakada et al. (Nakada) 60-235471 Nov. 22, 1985
(Japanese Kokai)
Claims 10 and 14 through 16 stand rejected under
35 U.S.C. § 103 as being unpatentable over Kotani in view of
Nakada and Shibata.
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