Appeal No. 97-0557
Application 08/371,040
USPQ 385, 388 (Fed. Cir.), cert dismissed, 468 U.S. 1228
(1984).
Rejection of Claims 13 through 17 under 35 U.S.C. § 102
The Examiner has rejected these claims as being
anticipated by Takemae. We take claim 13 as representative.
We have considered Appellants’ arguments [brief, pages 3 and
4] and Examiner’s position [answer, pages 3] in regard to
claim 13. We find that Takemae does not anticipate claim 13.
For example, Takemae does not show the limitation: “a
plurality of input buffers each located adjacent to and
connected to one of said plurality of circuit blocks;” (claim
13, lines 4 to 5). The Examiner contends that “[T]he claimed
‘plurality of input buffers’ correspond to the row and column
decoders 105-107 in array 1-1 and 1-2.” [Answer, page 3]. We
agree with the Examiner that each of elements 105-107 serve as
decoders for each word line and each bit line [column 4, lines
16 to 28], however the Examiner has not shown specifically a
plurality of input buffers each located adjacent to and
connected to one of said plurality of circuit blocks. The
Examiner has not presented any argument where such buffers are
-4-
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