Appeal No. 97-0557
Application 08/371,040
disclosed, explicitly or implicitly or inherently, in Takemae.
Appellants already admit in their disclosure [for example,
figure 1a] that there is a decoder DC in a line to each
circuit block. Takemae is primarily concerned with reducing
the total line width of the signal and power supply lines
linking the peripheral circuit areas and the pads and
bypassing the divided regular circuit areas, thereby
increasing the regular circuit area and hence increasing the
capacity of the memory [column 2, lines 18 to 29]. Takemae
offers little in the way of circuit connections in the manner
shown, for example, in figures 1 and 2 of the Appellants’
disclosure. We, therefore, conclude that the anticipation
rejection of claim 13 over Takemae is not sustainable. As for
the other independent claim 17, it also contains a
corresponding limitation, namely, “a plurality of input
buffers, each ... located proximate to and connected to one of
said decode circuits;” (claim 17, lines 6 to 7). Therefore,
the anticipation rejection of claim 17 is also not sustained.
Since claims 14 through 16 depend on claim 13 and contain at
least the claimed limitation discussed above regarding claim
13, their anticipation rejection over Takemae is also not
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