Appeal No. 1997-0621
Application 08/368,679
The disclosed invention relates to a high speed FIR
filter architecture that consumes less power than the existing
architectures, eases circuit implementation and improves
performance in terms of dynamic range and linearity. The
invention is further described by the following claim.
Representative claim 1 is reproduced as follows:
1. An FIR filter having an input signal and a filtered
output, comprising:
a plurality of multipliers, each said multiplier
including a first multiplier input, a second multiplier input
and an output, each said first multiplier input receiving a
signal representing an FIR coefficient;
a plurality of sample and hold circuits, each of said
plurality of sample and hold circuits including a first output
and operable to sample said input signal and hold the value of
said input signal on said first output for a predetermined
time;
a plurality of multiplexers, each comprising a plurality
of multiplexer inputs and a second output, at least two of
said second outputs each coupled to one of said second
multiplier inputs, and at least one of said plurality of
multiplexer inputs of a first predetermined number of
multiplexers coupled to said first output of a first of said
sample and hold circuits; and
a summer connected to said output of each of said
multipliers, said summer having an output which is said
filtered output of said FIR filter.
The reference relied on by the Examiner is:
Lish 5,050,119 Sept. 17, 1991
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