Appeal No. 97-0780
Application 08/330,265
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a memory means as recited in claim 11 . Second, the data in a tapped delay line is
written into the memory before it is read from the memory so that there is some time t as
di
recited in claim 11. Finally, when such delay lines are implemented in a digital fashion
such as by a shift register, data is clocked into the tapped delay line at some frequency
(the write frequency) and read from the delay line at some frequency (the read frequency).
Since claim 11 places no restrictions on the relationship of the time delay, write frequency
and read frequency, the tapped delay line of Argo (and appellant’s admitted prior art) when
implemented as a conventional digital shift register would have suggested the invention as
broadly recited in claim 11. Therefore, we sustain the examiner’s rejection of independent
claim 11.
With respect to dependent claim 12, the examiner simply asserts that Argo implies
a frequency down conversion process [answer, page 4]. We have been unable to find
such a teaching or suggestion in Argo. Therefore, we do not sustain the rejection of claim
12 or of claims 13 and 16 which depend from claim 12. With respect to dependent claims
14, 15, 17 and 18, appellant simply asserts that these claims add limitations to claim 11
[brief, page 12]. Such an assertion is insufficient to have the claims considered separately
for patentability. Since we have sustained the examiner’s rejection of independent claim
2See, for example, The New IEEE Standard Dictionary of Electrical and
Electronics Terms, Fifth Edition, Copyright 1993 by IEEE, Inc., page 323 [copy attached to
this decision].
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