Ex parte GIORGIO et al. - Page 9




          Appeal No. 97-2982                                         Page 9           
          Application No. 08/219,554                                                  


          employs Queue Descriptors to store data being transferred                   
          between the processors and devices.  No more than one Queue                 
          Descriptor is allocated to each device.  Col. 5, ll. 36-37.                 
          Because there is no more than a single Queue Descriptor for                 
          each device, the first processor of Fischer that clears                     
          certain data clears it for all the processors.  Thus, a                     
          processor in Fischer cannot clear ATTENTION DATA without                    
          disturbing the same ATTENTION DATA for any other processor as               
          claimed.                                                                    
                                                                                     
               ANSI does not remedy this defect.  The reference defines               
          the  Small Computer Interface Standard (SCSI) for attaching                 
          small computers together and to intelligent peripherals.  Abs.              
          A multiple initiator, multiple target configuration depicted                
          in the reference interfaces a plurality of host computers to a              
          plurality of targets via a plurality of controllers, i.e.,                  
          initiators.  Fig. 4-7.  The appellants explained operations                 
          under ANSI as follows.                                                      

               [O]nce a target's status is reported from the target                   
               through the initiator to the processor, that status                    
               information, normally stored in the target's                           
               controller, is cleared.  If another processor were                     







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