Appeal No. 1996-1431
Application 08/087,140
different time from the gate oxide of the peripheral transistors.
The disclosed invention provides a circuit in which the gate
oxide thicknesses of the memory cells, the peripheral transistors
and additional high voltage transistors are all made different
from each other.
Representative claim 76 is reproduced as follows:
76. A memory circuit comprising:
a) a high voltage transistor, said high voltage transistor
comprising:
a first set of first and second spaced-apart regions
formed in a silicon substrate, said first set of first and
second spaced-apart regions substantially forming a first
channel in said substrate therebetween;
a first gate insulator comprising a first oxide layer,
said first gate insulator disposed on said first channel;
a high voltage transistor control gate disposed on said
first gate insulator;
b) a peripheral transistor comprising:
a second set of first and second spaced-apart regions
formed in said silicon substrate, said second set of first
and second spaced-apart regions substantially forming a
second channel therebetween;
a second gate insulator comprising a second oxide
layer, said second oxide layer being a different layer from said
first oxide layer and having a different thickness than said
first oxide layer, said second gate insulator disposed on
said second channel;
a peripheral transistor control gate disposed on said
second gate insulator; and
2
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