Appeal No. 1996-3708
Application 07/474,742
The invention relates to an apparatus the architecture of
which permits the instantaneous realization of certain classes
of system in integrated circuit or discrete circuit form. On
pages 6 through 7 of the specification, Appellants disclose
that figure 1 shows a block diagram of the invention. The
apparatus includes a plurality of functional blocks 20 and a
central core. The communication between the blocks is via core
30. The core is the physical heart of the apparatus and is
responsible for interfacing with main communications bus 40.
The core interprets all data into and out of the apparatus,
including parametric, microcode and topological data, and
provides data routing via a non-blocking matrix switch.
Independent claim 1 is illustrative of the invention.
1. A programmable apparatus for interfacing with a
communications bus, said apparatus comprising:
a) a plurality of programmable signal processor means
having means for receiving and storing parameters and
microinstructions, and means for executing microinstructions,
each said programmable signal processor means for performing
an operation according to said microinstructions and said
parameters on signal data received by said programmable signal
processor means;
b) a core means comprising interface means for
interfacing with said communications bus, decoder means for
distinguishing between at least topological and parametric
data received by said core means over said communication bus,
2
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