Appeal No. 1996-3708
Application 07/474,742
the core with the processors (Engels DSPs) is met by the data
bus on the left side of Engels figure 1. On page 6 of the
answer, the Examiner states that the core’s decoder is met by
Engels HOST (Figure 1). The Examiner further states on page 7
of the answer that the claimed matrix switch of the core is
met by the LCAs of figure 2. On pages 7 and 8 of the answer,
the Examiner admits that Engels does not explicitly teach the
claimed communications bus, but asserts that “it would have
been self-evident/logical that Engels’ system provided for
such a network/bus interface to other processors.” The
Examiner supports this assertion by citing section 4.3 of
Engels which identifies that a bus (apparently the bus
identified in figure 1 with three lines labeled Address, Data
and Control) will connect the HOST and the DSP to I/O devices
which will allow other computers to be connected.
On page 15 of the appeal brief, Appellants argue that the
claimed function of the core differs from the Engels’ device.
Appellants assert on page 17 of the brief that the claims
recite a core means comprising interface means for interfacing
with the communication bus, decoder means for distinguishing
between topological and parametric data and matrix switching
6
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