Appeal No. 1997-0342
Application 08/229,135
a test data generating circuit to output test data, in a
first test mode, onto a bus to which a logic circuit under
test is connected to receive input data;
a selector having two inputs connected respectively to an
external terminal and the bus, for outputting data from said
external terminal in a second test mode and data on the bus in
said first test mode;
a register for transferring test data from the selector
onto the bus in the second test mode; and
a built-in self-test circuit for carrying out a test with
test data on the bus in the first test mode and in the second
test mode.
The Examiner relies on the following prior art:
Kahn et al. (Kahn) 5,167,020 Nov. 24,
1992
(Filed May 25, 1989)
Nozuyama 5,398,250 Mar.
14,
1995
(Effectively filed Jun. 22,
1989)
Claim 14 stands finally rejected under 35 U.S.C. § 103 as
being unpatentable over Kahn. In a new ground of rejection in
the Answer, the Examiner rejected claims 10, 15 and 16 under
35 U.S.C. § 103 as being unpatentable over Kahn in view of
Nozuyama.
Rather than reiterate the arguments of Appellant and the
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