Appeal No. 1997-0416
Application No. 08/125,406
While claim 14 is directed broadly to a method of stopping and starting a peripheral
bus clock, the language of claim 14 requires that the alternate bus master must generate
“an asynchronous clock request signal within an alternate bus master” and the peripheral
bus clock must be restarted “in response to said asynchronous clock request signal” and
then “generating a synchronous bus request signal within said alternate bus master to
request mastership of said peripheral bus after said peripheral bus clock signal has been
re-started, wherein said synchronous bus request signal is synchronous to said peripheral
bus clock signal.” The examiner combines various teachings in the rejection and
concludes that the combined teachings would meet the claimed invention, but the examiner
has not provided a convincing line of reasoning to achieve the claimed invention. While
each of the incremental steps of the process may have been generally known, the
examiner has not addressed the problem set forth in the specification with respect to
presence of alternative bus masters in a system and the need for a synchronous bus
request therefrom. In the discussion of the admitted prior art, the specification specifies
that if the peripheral bus clock is not operational then the bus request cannot be performed
in the prior art Figure 1. With the proposed combination of Herrig with respect to halting
the bus clock and restarting of the bus clock after physical manipulation of a board, there
would not be a signal requesting restart of the clock as required by claim 14. Moreover,
we find no motivation in Herrig for having an alternative bus master request a clock restart.
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