Appeal No. 1997-1247
Application 08/484,196
cells.
The trenches are dielectric filled and are segmented. The
invention is further illustrated below by claim 25.
25. A programmable memory device having a memory array
formed in a semiconductor body including a plurality of memory
cells arranged into rows and columns comprising:
a plurality of parallel and spaced apart slot trenches,
said slot trenches formed in sequences between said columns,
said slot trenches located at the crossings of diagonals with
respect to said rows and columns, each of said slot trenches
extending below said surface of said semiconductor body
between said columns;
a plurality of floating gates formed on a surfce (sic) of
said semiconductor body but separated from said surface of
said semiconductor body by a gate dielectric, said floating
gates positioned between said slot trenches;
a plurality of control gates, each of said control gates
extending over at least one of said floating gates and a
portion of said slot trenches, said control gates running
perepndicular (sic) to said slot trenches and parallel of each
other, exactly two of said control gates running over each of
said slot trenches away from the periphery of the array of
said rows and columns of memory cells; and
a plurality of source/drain regions formed in said
semiconductor body between said control gates and between said
slot trenches.
The references relied on by the Examiner are:
Gill et al. (Gill) 5,045,489 Sep. 3, 1991
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