Appeal No. 1997-1755
Application 08/163,447
semiconductor devices, each of said semiconductor devices
being spaced a predetermined distance from each other;
a plurality of packaging assembly input/output pins
arranged in spaced relationship for coupling signals to at
least some of said semiconductor devices from an external
source;
at least one clock input pin arranged with said
input/output pins for coupling a clocking signal to said
semiconductor devices;
common clock distribution means coupled between said
clock input pin and said clock input leads of said
semiconductor devices; and
fixed impedance means connected between said common clock
distribution means and a reference voltage, said impedance
means being physically located adjacent to said clock input
pin and between said clock input pin and said semiconductor
devices.
The references relied on by the Examiner are:1
Lee et al. (Lee) 4,639,615 Jan. 27, 1987
Lin et al. (Lin) 5,216,278 Jun. 1, 1993
Admitted Prior Art
Irwin, David, “Basic Engineering Circuit Analysis”, pages 332-
333 (Irwin).
1Even though Webster (the dictionary) and Irwin (the
circuit analysis book) do not appear in the statement of the
final rejection, the body of the final rejection and the
Appellants’ brief discuss these references. Therefore, we
treat them as a part of the final rejection for this appeal.
-3-
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007