Appeal No. 1997-2160
Application No. 07/548,709
algorithm …” However, as explained supra, it is our view that Yamazaki does, indeed, disclose such a
static scheduling means, as broadly claimed. We would also note that to the extent that appellants’
static “scheduling means” is something more than a predetermined schedule of which processor handles
which job, the instant specification offers scant detail as to this scheduling means, it not even being very
clear as to what disclosed structure comprises such “scheduling means.”
We will also sustain the rejection of claims 27 and 29 under 35 U.S.C. § 103 since they depend
from independent claim 26 and appellants present no separate arguments as to the merits of these
claims.
With regard to claim 28, appellants do argue the merits of this claim separately, i.e., that the
applied references do not show or suggest the claimed CPU and DSP instruction sets having “minimum
overlapping instructions.” The examiner’s response is to point to column 3, lines 24 et seq. of
Yamazaki to show that the DSP and CPU can proceed independently with different processing .
However, that portion of Yamazaki emphasizes that the CPU and DSP can process completely
different instruction sets and there would be no overlap occurring under those conditions. While the
claimed “minimum overlapping instructions” might be interpreted as no overlap, since no overlap is
certainly a minimum overlap, we do not think this would be a fair interpretation in view of appellants’
disclosure of some overlap of processing operations.
The examiner states that the “instructions in Yamazaki can be overlap [sic] also if the same
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