Appeal No. 1997-3162
Application 08/540,961
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134 from
the final rejection of claims 18, 2, and 3.
We reverse.
BACKGROUND
The invention relates to a field effect transistor
utilizing shallow trench isolation and a gate structure for
such a transistor which mitigates leakage current induced
along the edges of the device.
Claim 18 is reproduced below.
18. A field effect transistor isolated by shallow trench
isolation devoid of local oxidation of silicon (LOCOS)
isolation, said shallow trench isolation having a channel
width between first and second shallow trenches at first
and second shallow trench edges and a gate which extends
across said channel width between said first and second
shallow trenches, said gate having a first length at said
shallow trench edges and a second length less than said
first length between said shallow trench edges, said
first length and said second length being related such
that a threshold voltage, V , at said shallow trench edges
t
is substantially equal to V between said shallow trench
t
edges.
The Examiner relies on the following prior art:
Shimizu et al. (Shimizu) 5,466,623 November 14,
1995
(effective filing date June 30,
1988)
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