Appeal No. 1997-3162
Application 08/540,961
Kikuchi2 4-207763 March 4,
1994
(Japanese Unexamined Published Patent Application
(Kokai))
Kikuchi discusses the prior art in connection with
figure 4, which teaches providing a gate electrode pattern 3
across an active source-drain diffusion region 5, 6 surrounded
by LOCOS-type isolating-insulating film 2. Such a transistor
has two problems (translation, page 3): (1) the actual
channel width L2 at the end of the active region is narrower
than the actual channel width L1 at the center of the active
region due to faster diffusion of the layers 5, 6 because of
oxidation stresses, which causes the electric field to become
concentrated and causes leakage current and a short circuit
between the source and drain due to punch-through; and (2) the
pattern width of the silicon pattern is narrower at the end of
the gate area 3c, lead area 3b, and protrusion area 3d than at
the center of the gate area 3c due to the difference in
exposure caused by the difference in height of the film 2,
which causes the channel width to be narrow and may cause the
Our understanding of Kikuchi is based on a translation2
prepared by the Patent and Trademark Office, a copy of which
accompanies this decision.
- 3 -
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007