Appeal No. 1997-3273
Application No. 08/397,910
includes a computer in which a memory error address is stored
in either a low priority or a high priority error queue, and
the computer clock is disabled in response to a detected
overflow in the high priority queue. Claim 1 is illustrative
of the claimed invention, and it reads as follows:
1. A method for prioritizing and handling memory errors in a
computer having a memory and a processing unit, the computer
operating responsive to a clock, the method comprising the
steps of:
detecting the occurrence of a memory error;
identifying the type of memory error as either a first
type or a second type;
storing in a first error queue an address of the memory
error if the error is a first type of error;
storing in a second error queue an address of the memory
error if the error is a second type of error;
detecting an overflow if more than a predetermined number
of addresses are stored in the second error queue;
disabling the clock responsive to the detected overflow.
The prior art references of record relied upon by the
examiner in rejecting the appealed claims are:2
2May, Jr., PN 3,573,745, Giroir et al., PN 4,980,852, and Renault et
al., PN 5,471,510, are all cited in the prior art section of the Examiner's
Answer but were not applied in any rejection. Therefore, we have not
considered them.
2
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