Appeal No. 1997-3426
Application 08/373,052
slave by means of halt, clear, initiate, and interrupt
commands sent via input/output 14 causing the slave to execute
test programs (col. 8, lines 41-44). "Underwood et al. are
thus not seen to expressly disclose or suggest that the master
processor assumes control over the signal lines of the slave
processor." (Br14.)
In response, the Examiner basically repeats the
statements in the Final Rejection (EA10).
Appellants reply (RBr7):
The transfer switch 16 appears to control access to the
memories 24-28 for processors 10 and 12 (col. 3,
lines 39-46). It is not seen where the transfer switch
16 assumes control over signal lines of the processors 10
and 12 to perform a diagnostic-related function.
Furthermore, a single-stepped processor, although being
single-stepped through instructions by another processor,
would still have control over its own signal lines while
executing each instruction.
We agree with Appellants that Underwood does not disclose
the master processor assuming control over the signal lines of
the slave processor. The slave executes the programs, not the
master. Moreover, the processors 10 and 12 do not even
communicate directly, but communicate indirectly by placing
instructions or data in either the input/output 14 or one of
the memories 24, 26, and 28 (col. 3, lines 13-17). Thus, one
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