Appeal No. 1997-3436 Page 3
Application No. 08/432,884
coupled between the latch circuit and each of the local data
write driver circuits to selectively apply an output signal
from a local data driver circuit to the latch circuit and the
corresponding bit line.
Claim 14, which is representative for our purposes,
follows:
14. A sense amplifier arrangement for an
integrated circuit memory comprising, for each of a
plurality of sense amplifiers:
a sense amplifier latch circuit having a pair of
nodes to which respective bit lines may be coupled;
a local column read amplifier responsively
coupled to the sense amplifier, and receiving at
least one data read signal; and
a local data write driver circuit coupled to
receive write data during a write operation at a
gate electrode of a transistor in said data write
driver circuit and to apply a signal based upon
receiving said write data to one of said latch
circuit nodes.
The reference relied on in rejecting the claims follows:
Ohsawa 5,220,527 June 15, 1993
(filed Mar. 29,
1991).
Claims 14, 18, and 31-44 stand rejected under 35 U.S.C.
§ 102(e) as anticipated by Ohsawa. (Examiner’s Answer at 2.)
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