Appeal No. 1997-3743
Application 08/419,166
Mathews, thus necessitating reliance upon what was known in the
art.
According to the examiner's rejection, the second bus is bus
13 connecting the programming terminal 11 to the primary rack 12
in Figure 1 by means of UART 28 in Figure 2. Column 4, lines 19
through 23 indicate that the port UART 28 may be coupled to other
types of serial devices for the exchange of data with the entire
processor module 20 shown in all of Figure 2.
Claim 9 only recites a peripheral unit and an external unit
that appear to be indirectly interconnected. In contrast to the
assertion at page 5 of the brief there are no claimed separate
peripheral interfaces and a communication interface in claim 9 on
appeal. Only “a busable programming interface” is recited.
Broadly speaking, according to the examiner's rationale and a
reliance upon Mathews, it appears that the first communication
processor 21 as well as the general purpose processor 60 along
with the second communication processor 70 provide clear
indications in Figure 2 of this busable programming interface in
this reference notwithstanding the additional capability of
input/output communications through the I/O rack interface
circuit 38 further shown in detail in Figure 4, which in turn
provides two separate programmable processing elements for
5
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