Appeal No. 1997-4092
Application No. 08/181,404
We have carefully considered the entire record before us,
and we will reverse the 35 U.S.C. § 102(e) rejection of claims
1 through 26 and 30 through 51.
Appellants argue (Brief, pages 10 and 11) that “it is
important to point out that Hollerbauer is directed to a
dynamic RAM, while the claimed invention specifically recites
a nonvolatile semiconductor memory system that includes a
nonvolatile memory cell array and a flag cell array including
a plurality of nonvolatile flag cells.” Appellants recognize
that claims 33 through 51 are not limited to a nonvolatile
memory cell array and a plurality of nonvolatile flag cells
and argue (Brief, page 19) that these claims include “flag
cells each storing refresh status data corresponding to a
respective one of the refresh blocks.” “In complete contrast
to the claimed invention, Hollerbauer teaches use of a
plurality of registers that store start and stop addresses
corresponding to portions of the dynamic RAM where data is
stored” (Brief, page 19).
We agree with appellants’ arguments. The examiner’s
statement (Answer, page 3) that “[e]ven though Hollerbauer’s
memory device is preferably constructed as a dynamic RAM
3
Page: Previous 1 2 3 4 5 6 7 8 Next
Last modified: November 3, 2007