Appeal No. 1997-4350 Page 2
Application No. 08/574,848
The invention is directed to a computer system employing a
duplicate tag store having duplicates of the main memory
addresses contained in a CPU cache tag store. The invention is
said to minimize traffic on the system bus and the CPU bus by
eliminating bus transactions for memory requests to memory
locations not present in the duplicate cache store. A bus
transaction is generated only for memory requests to locations
present in the duplicate tag store.
Independent claim 4 is reproduced as follows:
4. A computer system comprising:
a main memory having memory locations identified by main
memory addresses;
a processor unit, coupled to the main memory, including
a CPU for processing data stored in the memory locations;
a CPU cache memory for storing the processed data; and
a CPU cache tag store containing the main memory addresses
of the processed data stored in the CPU cache memory;
an input/output bus, coupled to the processor unit;
a plurality of input/output devices connected to the
input/output bus for issuing memory requests containing main
memory addresses;
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007