Appeal No. 1997-4350 Page 3
Application No. 08/574,848
a duplicate tag store, coupled directly to the
input/output bus, having duplicates of the main memory
addresses contained in the CPU cache tag store;
means for comparing an address in one of the memory
requests with the addresses in the duplicate tag store; and
means, responsive to an address in said one of the memory
requests matching an address in the duplicate tag store, for
issuing an invalidate request to ensure that the most current
value of the data is accessed.
The examiner relies on the following references:
Hartwell et al. (Hartwell) 4,858,234 Aug. 15,
1989
Milia et al. (Milia) 5,226,146 Jul. 6,
1993
(effective filing date Oct. 28, 1988)
Claims 4 and 5 stand rejected under 35 U.S.C. 103 as
unpatentable over Milia in view of Hartwell.
Reference is made to the brief and answer for the
respective positions of appellants and the examiner.
OPINION
We reverse.
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