Appeal No. 1998-0598
Application No. 08/278,864
5 through 11 is reversed.
Shimpuku discloses a maximum likelihood decoding
apparatus (Figures 4 and 5) in which the output of the
synchronization detecting circuit 27 inputs both a symbol
concluding unit 29 and a viterbi decoding unit 30. According
to the examiner (paper number 11, pages 2 and 3), Shimpuku
discloses all of the limitations of claim 1 except for the
partial response encoder.
For such a teaching, the examiner turns to Kanota (Figure 5),
and states (paper number 11, page 3) that “[i]t would have
been obvious to one of ordinary skill in the art at the same
time the invention was disclosed to modify the teachings of
Shimpuku et al. to include the teachings of Kanota et al.,
motivation being to carry out channel coding satisfactorily
and to efficiently suppress data redundancy.”
Appellants argue (Brief, page 12) that “Shimpuku and
Kanota fail to suggest any type of means for modeling an
impulse response and furthermore fail to suggest means for
modeling an impulse response ‘based on the synchronizing
signal data part.’”
We agree with appellants’ argument. Even if we assume
5
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