Appeal No. 1998-1469
Application No. 08/351,045
sets of data that are not encoded, which requires the use of synchronizing circuit (8) in order to
synchronize the operations of decoder (7) with the operations of encoder/decoder (5). The
examiner responds by asserting (answer, page 4) that by modifying comparator (23) of Ichijo to use
coded signals, the skilled artisan could delete decoder (7) and simplify the operation of Ichijo since,
according to the examiner, this would constitute the omission of an element and its corresponding
function.
In making our determination as to whether or not Ichijo teaches or fairly suggests the
modifications advanced by the examiner to arrive at the claimed invention, we first turn to the disclosure
of Ichijo. We find that in Ichijo, incoming data from an external line is stored in second order buffer
memory (13). When a start signal is supplied to timing signal generator (14), signal OPEN (Figure 2D)
becomes high to transfer data from second order buffer memory (13) to first order memory block (10)
(col. 4, lines 40-44). First order memory block (10) includes blocks g g with each block having the
1-8,
capacity to store digital data for one frame recorded on a magnetic tape when rotary drum 1 makes a
complete rotation (col. 2 line 68 - col.3, line 2). Buffer (9) is a latch for transferring data from first
order memory (10) to encoder/decoder (5), which encodes the digital data to be recorded (col. 2, lines
50-51). RF signal processor (4) amplifies the signal which is recorded on a magnetic tape by recording
heads (2a, 2b). Reproduction heads (also called ascertaining heads col. 2, lines 41-43) reproduce the
data recorded on the magnetic tape by recording heads (2a, 2b). After amplification by RF amplifier
(6), the amplified data is decoded and synchronized with the encoding/decoding operations of
encoder/decoder (5) by synchronization circuit (8). Comparator (23) compares the digital data
reproduced and decoded through ascertaining heads (3a, 3b) from the magnetic tape with digital data
read via buffer (11) from first order block memory (10) and supplies the result to timing signal
generator (14) (col. 3, lines 52-56). When there is a difference between both inputs to the
-7-
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