Appeal No. 1998-1802
Application 08/245,786
The disclosed invention pertains to the arrangement of
a data processor, a level 2 (L2) cache and a main memory
within a computer system. More particularly, the invention
relates to the integration and interconnection of these
components in a manner to reduce the time it takes to access
data from the L2 cache or from the main memory and provide
such data to the processor.
Representative claim 1 is reproduced as follows:
1. A computer system including a processing unit, L2
cache and memory, comprising:
a storage control unit including an integrated cache
controller and memory controller for controlling operations of
said L2 cache and said memory, respectively;
means for simultaneously initiating a first operation to
retrieve information from said L2 cache and a second operation
to retrieve information from said memory;
means for determining if information required by said
processing unit is stored in said L2 cache; and
means for aborting said second operation by providing a
stop memory operation signal directly from said cache
controller to said memory controller concurrent with a
determination that said information is in said L2 cache;
wherein said second operation is aborted before any
request signals are output to said memory and said memory
continues operations independent of said second operation.
The examiner relies on the following references:
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